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The motivation to study this non-classical CMOS device is necessary to face with the ITRS constraints. In the ITRS roadmap, the gate length of devices are being scaled down rapidly but this rapid scaling is not in pace with the relatively slow scaling of the gate equivalent oxide thickness which leads to a degradation in the performance of the transistor. One of the solutions to this problem is the use of non-classical devices, such as the Gate-All-Around (GAA) MOSFET. Owing to the flexibility of SOI technology, these novel devices can be adapted to this technology bringing along with it the benefit of SOI technology. One of the main advantage of building this GAA device on SOI technology is that it offers the possibility whereby the second gate is easily built into the back of the device. The objective of this research can be divided into three parts ; the first is to study the feasibility of the various fabrication process for this GAA device, the second to analyse the electrical characteristics of these fabricated GAA devices from DC characteristics up to 110 GHz and the third one is the use of commercial numerical simulation softwares (IE3D, Silvaco) in order to describe the physics of these novel devices. In this study, these different structures shows advantages and disadvantages when used in either analog or RF applications. The graded-channel structure has shown that it is advantageous when used in high performance analog circuits. The advantages of this structure is further enhanced when it is combined with the double-gate structure, forming a double-gate graded channel SOI MOSFET. Optimizing in terms of doping level along the channel of the graded-channel is important to yield good electrical results. In order for these devices to be successful commercially, it is important that they are compatible with the fabrication technology and trends available today and in the near future. To confirm that these devices can be adapted into today's and tomorrow's technology, we have shown that these they are easily adaptable in the current technology. Multiple-gate devices are a new group of devices which have been identified by ITRS as potential devices to meet the demands in the future. In this study, we have shown that these multiple-gate devices do indeed show improved short-channel effects and improved analog and RF characteristics when compared to the single-gate devices in existence.
|AUTEUR||Ming Chung Tsung|
|DATE DE PUBLICATION||2007-Jan-01|
|TAILLE DU FICHIER||9,69 MB|
|NOM DE FICHIER||Graded Channel and Multiple-Gate Devices in SOI Technology for Analog and RF Applications.pdf|
Abstract. In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction.
Simulation, Fabrication and Characterization of Advanced MOSFETs: Graded-Channel and Multiple-Gate Devices in SOI Technology for Analog and RF Applications.: Tsung Ming Chung: 9783639146004: Books - Amazon.ca
Mozart Correspondance - Coffret en 7 volumes : Tome 1, Correspondance 1756-1776, Tome 2, Correspondance 1777-1778 ; Tome 3, Corespondance 1778-1781 ; Tome 4, Correspondance 1782-1785 ; Tome 5, 1786-1791 ; Tome 6, 1792-1825 ; Tome 7, Correspondance VII.pdf